This invention generally relates to isolation for semiconductor structures such as integrated circuits. More particularly it relates to a layout for isolation that reduces the cost and process complexity of trench isolation. Even more particularly, it relates to a layout for isolation that provides narrow regions of isolation around active areas and under first level conductors.
Isolation is provided in a semiconductor between transistors on a semiconductor chip to prevent unwanted electrical connections therebetween.
Local oxidation of silicon (LOCOS) has long been the conventional process for fabricating isolation, and it has the advantage of being both relatively inexpensive and capable of providing isolation over wide areas of a chip. LOCOS has several disadvantages, however, among them the formation of a bird""s beak that increases the horizontal space of the isolation, reducing the density of devices on a chip.
Because of its more vertical sidewalls and more planar surface trench isolation provides significant advantage over LOCOS in the quest for providing a high density of integrated circuits. Trench isolation schemes are therefore finding increasing use in semiconductor processing. However, because of the difficulty of planarizing, trench isolation is more complex and expensive to process.
Trench isolation process complexity is evident from a brief description of the conventional shallow trench isolation (STI) process. First, thick silicon nitride is deposited on thin silicon dioxide on the semiconductor surface. Then, in a first photolithography step, a mask is formed in the layers of insulator defining the areas where STI is desired. Next, the semiconductor is etched, using a reactive ion etch (RIE) process, to form shallow trenches. A thin layer of silicon dioxide is then thermally grown and a conformal silicon dioxide layer is deposited, filling the shallow trenches.
A lengthy series of steps, such as the sequence described below, is then used solely to planarize the surface. The typical planarization process is quite complex because (1) the oxide deposition is usually conformal, and therefore narrow areas of isolation may be at a higher level than wide areas of isolation; and (2) wide areas of isolation polish much more quickly than narrow areas, a problem known as dishing.
Dishing is a problem, first because oxide in these large areas of STI is thinner than in narrow areas, and second because in regions having a low density of devices, the nitride polish stop layer over small, isolated active area regions may be completely polished off, and then the active area may get polished down, introducing potential damage to the semiconductor crystal.
To overcome these difficulties the planarization steps may involve applying a planarizing material, such as spin-on-glass or photoresist. For example, one conventional process uses two photoresist applications and a masking step for planarizing. In addition, tight control over plasma etching and chemical-mechanical polishing steps are needed, all adding significantly to the process complexity of trench isolation compared to conventional LOCOS. The photoresist application and masking step planarizes by providing photoresist exclusively in the isolation areas (the low areas), and removing photoresist from the active areas (the high areas). The resist thickness is designed to equal the shallow trench depth, so the surface of the remaining resist is roughly coplanar with the surface of the exposed oxide film over active areas. The next photoresist layer is spun-on (but no expose or develop step is used) to further smooth out local variations in the developed resist pattern, resulting in a photoresist and oxide surface that is both locally and globally planar. An RIE process then etches back both the photoresist and the oxide at about the same rate to a point below irregularities in the oxide, rendering the wafer surface largely planar. A final touch-up chemical-mechanical polish (CMP) is then used to remove any local irregularities and complete the oxide removal over active areas.
Even with this process complexity, the results of the conventional STI process are frequently unsatisfactory. Substantial dishing is still found in areas having a large expanse of STI or a low density of devices. Furthermore, the process complexity introduced to overcome dishing increases cost and cycle time and reduces yield. Thus, an alternate scheme for providing trench isolation, without the need for a complex series of planarization steps, is needed and is provided by the following invention.
It is therefore an object of the present invention to reduce the cost and complexity of STI and to increase the yield of product having STI.
It is a further object of the present invention to avoid dishing of areas with a low density of devices without adding process complexity.
It is another object of the present invention to eliminate extra photoresist application and exposure steps during STI processing.
It is another object of the present invention to provide isolation both horizontally between active semiconductor areas and vertically between a first level of conductor and the silicon surface.
It is a feature of the present invention that large expanses of STI are replaced with inactive semiconductor areas, there being narrow rings of STI immediately surrounding active semiconductor areas and STI paths underlying first level conductors, the paths little wider than the conductors.
It is a feature of the present invention that the design of an isolation mask includes the layouts of active semiconductor areas and of first level conductors, including gate conductors and local interconnects, where the first level conductors extend beyond active semiconductor areas.
It is an advantage of this invention that dishing of active semiconductor areas and STI is eliminated by design rather than process.
It is an advantage of this invention that the cost, complexity, defects, and cycle time of STI processing are significantly reduced, while yield is improved.
It is an advantage of this invention that process window during chemical-mechanical polishing of STI is increased.
These and other objects of the invention are accomplished by the isolation structure of the present invention. The structure includes a semiconductor substrate having an isolation ring having an inside edge and an outside edge. An active semiconductor area borders the inside edge, and the active semiconductor area includes a device. An inactive semiconductor area borders the outside edge. A trench isolation path extends from the outside edge to a location on the substrate outside the isolation ring. The inactive semiconductor area borders at least two sides of the isolation path. A first level conductor is on the isolation path. The first level conductor electrically connects or capacitively couples the device to the location. The isolation path electrically insulates the conductor from the inactive semiconductor.